Both clocks and customisation are described in the MIG user guide for the. Note that in 7 Series, the user can pick the. Clock frequency of MIG.

There are two key clocks in a MIG design: • sys_clk (including sys_clk_p and sys_clk_n) -- this is the clock input to the PLL which generates all the clocks used in the MIG core. By default, the MIG-generated code presumes that this input clock is the same frequency as the memory clock. It is up to the designer to customise the MIG-generated code, including re-configuring the PLL to accommodate a different source clock frequency. • memory clock (including mcbx_dram_ck and mcbx_dram_ck_n) -- this is the clock output to the DRAM. It is a DDR clock -- its frequency is half the DRAM transfer rate. A DDR3-800 memory transfers data at 800Mbits/second (per pin) using a 400MHz memory clock. There are other clocks generated by the PLL embedded in the MIG-generated code, including: • The MIG-generated logic is clocked at 2x the memory clock frequency.

MIG 7 Series and Virtex-6 DDR2/DDR3. This Answer Record is a part of the Xilinx MIG. Of the Virtex-6 Memory Interface Solutions User Guide and in the 7 Series. The Xilinx® 7 series FPGAs memory interface solutions. See the release notes for MIG. Refer to the Virtex-7 FPGAs Data Sheet. User Guide (UG586) for more.

• There is a calibration clock for calibrating (de-skewing) the IOs connected to the external DRAM. In addition, when customising the MIG-generated code, you can add outputs to the PLL for general clock generation purposes (avoiding the need to consume an additional PLL or DCM). Both clocks and customisation are described in the MIG user guide for the specific device family you are targeting. -- Bob Elkind. SIGNATURE: README for newbies is here: Summary: 1.

Read the manual or user guide. Have you read the manual? Can you find the manual? Search the forums (and search the web) for similar topics.

Do not post the same question on multiple forums. Do not post a new topic or question on someone else's thread, start a new thread! Students: Copying code is not the same as learning to design. 6 'It does not work' is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). You are not charged extra fees for comments in your code.

I am not paid for forum posts. If I write a good post, then I have been good for nothing. • sys_clk (including sys_clk_p and sys_clk_n) -- this is the clock input to the PLL which generates all the clocks used in the MIG core. By default, the MIG-generated code presumes that this input clock is the same frequency as the memory clock. It is up to the designer to customise the MIG-generated code, including re-configuring the PLL to accommodate a different source clock frequency.

Note that in 7 Series, the user can pick the desired input clock right in the GUI. No need for the designer to modify the generated code to change the input clock frequency. SIGNATURE: README for newbies is here: Summary: 1. Read the manual or user guide. Have you read the manual?

Can you find the manual? Search the forums (and search the web) for similar topics. Do not post the same question on multiple forums. Do not post a new topic or question on someone else's thread, start a new thread!

Students: Copying code is not the same as learning to design. 6 'It does not work' is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). You are not charged extra fees for comments in your code. I am not paid for forum posts. If I write a good post, then I have been good for nothing. Mr Bean Dress Up Games on this page.

>There is one more interest for designers to hand-edit MIG-generated code: Providing additional clock outputs >from the PLL used in the MIG design (rather than 'burn' an additional PLL). Has this capability also been >added to the Gen 7 version of MIG?

No, not there. It is an interesting idea. To make it truly hands free, we would need to give access to a limited clocking wizard that would know what can and can't be changed for the memory interface and what is and isn't allowed with the remaining outputs.